Invention Grant
- Patent Title: Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
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Application No.: US16821746Application Date: 2020-03-17
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Publication No.: US11024630B2Publication Date: 2021-06-01
- Inventor: Scott E. Sills
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L27/108 ; H01L49/02 ; H01L27/11507

Abstract:
A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.
Public/Granted literature
Information query
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