Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate

Invention Grant

US10998441B2 Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate 有权

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Patent Title: Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate
Application No.: US15786037

Application Date: 2017-10-17
Publication No.: US10998441B2

Publication Date: 2021-05-04
Inventor: Kangguo Cheng , Nicolas J. Loubet , Xin Miao , Alexander Reznicek
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Applicant Address: US NY Armonk
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee Address: US NY Armonk
Agency: Tutunjian & Bitetto, P.C.
Agent Randall Bluestone
Main IPC: H01L29/78
IPC: H01L29/78 ; H01L27/092 ; H01L21/8238

Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate

Abstract:

A method of forming a semiconductor device that includes forming a strain relaxed buffer (SRB) layer atop a supporting substrate, and epitaxially forming a tensile semiconductor material atop a first portion of the strain relaxed buffer layer (SRB) layer. A second portion of the SRB layer is then removed, and a semiconductor material including a base material of silicon and phosphorus is formed atop a surface of the supporting substrate exposed by removing the second portion of the SRB layer. A compressive semiconductor material is epitaxially forming atop the semiconductor material including the base material of silicon and phosphorus. Compressive FinFET structures can then be formed from the compressive semiconductor material and tensile FinFET structures can then be formed from the tensile semiconductor material.

Public/Granted literature

US20180053853A1 STRAINED SILICON COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INCLUDING A SILICON CONTAINING TENSILE N-TYPE FIN FIELD EFFECT TRANSISTOR AND SILICON CONTAINING COMPRESSIVE P-TYPE FIN FIELD EFFECT TRANSISTOR FORMED USING A DUAL RELAXED SUBSTRATE Public/Granted day:2018-02-22

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L29/00	专门适用于整流、放大、振荡或切换，并具有至少一个电位跃变势垒或表面势垒的半导体器件；具有至少一个电位跃变势垒或表面势垒，例如PN结耗尽层或载流子集结层的电容器或电阻器；半导体本体或其电极的零部件（H01L31/00至H01L47/00，H01L51/05优先；除半导体或其电极之外的零部件入H01L23/00；由在一个共用衬底内或其上形成的多个固态组件组成的器件入H01L27/00）
H01L29/66	.按半导体器件的类型区分的
H01L29/68	..只能通过对一个不通有待整流、放大或切换的电流的电极供给电流或施加电位方可进行控制的（H01L29/96优先）
H01L29/76	...单极器件
H01L29/772	....场效应晶体管
H01L29/78	.....由绝缘栅产生场效应的