Invention Grant
- Patent Title: Fabrication of a vertical fin field effect transistor with reduced dimensional variations
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Application No.: US16234974Application Date: 2018-12-28
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Publication No.: US10998240B2Publication Date: 2021-05-04
- Inventor: Kangguo Cheng
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: TESSERA, INC.
- Current Assignee: TESSERA, INC.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/02 ; H01L21/308 ; H01L27/088 ; H01L21/3065 ; H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L29/786 ; H01L21/8238 ; H01L21/266 ; H01L21/762 ; H01L27/108 ; H01L27/11
Abstract:
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
Public/Granted literature
- US20190139832A1 FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS Public/Granted day:2019-05-09
Information query
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