The present disclosure discloses a memory access interface device. A clock generation circuit generates a command reference clock signal. Each of the access signal transmission circuits adjusts a phase and a duty cycle of one of access signals from a memory access controller according to the command reference clock signal to generate one of output access signal including an output external read enable signal to activate a memory device and an output internal read enable signal. The data reading circuit samples a data signal from the activated memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller. The multiplexer generates the sampling signal according to the output internal read enable signal under a SDR mode and generates the sampling signal according to a data strobe signal from the activated memory device under a DDR mode.