Invention Grant
- Patent Title: FeRAM-DRAM hybrid memory
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Application No.: US16440549Application Date: 2019-06-13
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Publication No.: US10998046B2Publication Date: 2021-05-04
- Inventor: Kazuhiko Kajigaya
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C14/00 ; G11C11/22 ; G11C11/4091 ; G11C11/4093 ; G11C7/10 ; G11C7/22 ; G11C7/06 ; G11C7/14 ; G06F12/02 ; G11C11/00 ; G11C11/4096

Abstract:
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.
Information query