One or more processors receive one or more variations to one or more first instruction elements in a first instruction set that indicate one or more second instruction elements of a second instruction set. One or more processors determine whether the one or more first instruction elements exceed a threshold of variability. One or more processors determine whether the one or more first instruction elements and the one or more second instruction elements are substantially equivalent. One or more processors determine whether a first outcome of the first instruction set is substantially similar to a second outcome of the second instruction set.