For implementing a logic design, a method encodes a logic design as a linear array that includes a plurality of logic states. The method calculates a combination map for a state transition between a start state and an end state of the plurality of logic states using the linear array to reduce computational overhead. In addition, the method identifies undefined binary input variable transitions for the state transition on the combination map. The method resolves the undefined binary input variable transitions in the linear array. The method generates a final logic design comprising Boolean logic from the linear array with the resolved binary input variable transitions. The method implements the final logic design in hardware by generating semiconductor gates that implement the Boolean logic.