In an embodiment, a method of forming a delay line circuit may include forming a first ferro-electric material between a first conductor and a second conductor wherein the first conductor and the second conductor have a first resistivity. The first conductor may be configured to receive a d.c. bias signal. An embodiment may include forming a third conductor overlying the second conductor, the third conductor having a second resistivity that is less than the first resistivity, the third conductor connected to the second conductor at least at a plurality of points along a length of the third conductor. The third conductor may be configured to receive an RF signal and conduct the RF signal along the length of the third conductor.