Invention Grant
- Patent Title: Semiconductor structure having both gate-all-around devices and planar devices
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Application No.: US16393166Application Date: 2019-04-24
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Publication No.: US10971630B2Publication Date: 2021-04-06
- Inventor: Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L29/786 ; H01L29/423 ; H01L21/8238 ; H01L27/092 ; H01L29/775

Abstract:
An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate. Gate dielectric layers of the GAA nanowire transistors and the GAA nanosheet transistors have substantially the same thickness which is smaller than the thickness of the gate dielectric layer of the planar devices. The channel width of the planar devices is greater than the channel width of the GAA nanosheet transistors, which is greater than the channel width of the GAA nanowire transistors.
Public/Granted literature
- US20200343387A1 Semiconductor Structure Having Both Gate-All-Around Devices and Planar Devices Public/Granted day:2020-10-29
Information query
IPC分类: