Invention Grant
- Patent Title: Dummy dielectric fin design for parasitic capacitance reduction
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Application No.: US16448704Application Date: 2019-06-21
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Publication No.: US10971605B2Publication Date: 2021-04-06
- Inventor: Kuo-Cheng Ching , Chih-Hao Wang , Shi Ning Ju , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/417 ; H01L29/78 ; H01L29/51 ; H01L27/092

Abstract:
A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.
Information query
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