Invention Grant
- Patent Title: Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization
-
Application No.: US16296911Application Date: 2019-03-08
-
Publication No.: US10943989B2Publication Date: 2021-03-09
- Inventor: Heng Wu , Ruqiang Bao , Junli Wang , Lan Yu , Dechao Guo
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/165 ; H01L21/02 ; H01L29/78

Abstract:
A method for fabricating a semiconductor device includes forming a first inner spacer layer along a substrate and a nanosheet stack disposed on the substrate, performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer, forming a second inner spacer layer along the hardened inner spacer, and removing material to form inner spacers by performing an inner spacer etch.
Public/Granted literature
- US20200287021A1 GATE TO SOURCE/DRAIN LEAKAGE REDUCTION IN NANOSHEET TRANSISTORS VIA INNER SPACER OPTIMIZATION Public/Granted day:2020-09-10
Information query
IPC分类: