Invention Grant
- Patent Title: Method for fabricating semiconductor device
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Application No.: US16403251Application Date: 2019-05-03
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Publication No.: US10943912B2Publication Date: 2021-03-09
- Inventor: Yong Li
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai; CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai; CN Beijing
- Agency: Anova Law Group, PLLC
- Priority: CN201611248887.1 20161229
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L21/8238 ; H01L27/02 ; H01L27/092 ; H01L29/423

Abstract:
A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.
Public/Granted literature
- US20190259766A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2019-08-22
Information query
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