Invention Grant
- Patent Title: Method of forming three-dimensional integrated circuit having ESD protection circuit
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Application No.: US16050694Application Date: 2018-07-31
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Publication No.: US10943897B2Publication Date: 2021-03-09
- Inventor: Wei Yu Ma , Chia-Hui Chen , Kuo-Ji Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L23/60
- IPC: H01L23/60 ; H01L27/02 ; H01L27/06 ; H01L29/861 ; H01L23/48
Abstract:
A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.
Public/Granted literature
- US20180337169A1 METHOD OF FORMING THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING ESD PROTECTION CIRCUIT Public/Granted day:2018-11-22
Information query
IPC分类:
