Invention Grant
- Patent Title: Staggered die stacking across heterogeneous modules
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Application No.: US16853201Application Date: 2020-04-20
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Publication No.: US10943887B2Publication Date: 2021-03-09
- Inventor: Yen Hsiang Chew
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Priority: MYPI2017704785 20171213
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L25/065 ; H01L23/538 ; H01L21/56 ; H01L25/00 ; H01L21/027 ; H01L25/10 ; H01L21/48

Abstract:
An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
Public/Granted literature
- US20200251446A1 STAGGERED DIE STACKING ACROSS HETEROGENEOUS MODULES Public/Granted day:2020-08-06
Information query
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