Invention Grant
- Patent Title: IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures
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Application No.: US16553962Application Date: 2019-08-28
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Publication No.: US10943882B1Publication Date: 2021-03-09
- Inventor: Jayprakash Chipalkatti , Zuhair Bokharey , Don Templeton , Brian Schieck , Julie Lam , Prashant Pathak
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/66

Abstract:
An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
Public/Granted literature
- US20210066227A1 IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE CTE MISMATCH AT REFLOW TEMPERATURES Public/Granted day:2021-03-04
Information query
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