Method for optimizing a critical dimension for double patterning for NAND flash
Abstract:
The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.
Information query
Patent Agency Ranking
0/0