Invention Grant
- Patent Title: Different word line programming orders in non-volatile memory for error recovery
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Application No.: US16709709Application Date: 2019-12-10
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Publication No.: US10943662B1Publication Date: 2021-03-09
- Inventor: Daniel Linnen , Jayavel Pachamuthu , Kirubakaran Periyannan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/10 ; G11C16/04 ; G11C16/14 ; H01L27/11582 ; G11C11/56

Abstract:
An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.
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