Invention Grant
- Patent Title: Memory processing unit
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Application No.: US15986347Application Date: 2018-05-22
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Publication No.: US10943652B2Publication Date: 2021-03-09
- Inventor: Wei Lu , Mohammed A. Zidan
- Applicant: The Regents of The University of Michigan
- Applicant Address: US MI Ann Arbor
- Assignee: The Regents of The University of Michigan
- Current Assignee: The Regents of The University of Michigan
- Current Assignee Address: US MI Ann Arbor
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C11/56 ; G06F7/544 ; G06F17/16

Abstract:
An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.
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