A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.