Read latency improvement method and memory system thereof
Abstract:
A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.
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