Invention Grant
- Patent Title: Read latency improvement method and memory system thereof
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Application No.: US16517232Application Date: 2019-07-19
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Publication No.: US10943634B2Publication Date: 2021-03-09
- Inventor: Hui-Sug Jung
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2018-0151629 20181130
- Main IPC: G11C11/22
- IPC: G11C11/22 ; G06F11/10 ; G11C29/50 ; G06F11/07

Abstract:
A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.
Public/Granted literature
- US20200176045A1 MEMORY SYSTEM AND OPERATING METHOD THEREOF Public/Granted day:2020-06-04
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