An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.