Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.