Invention Grant
- Patent Title: Molded wafer level packaging
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Application No.: US16722376Application Date: 2019-12-20
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Publication No.: US10916485B2Publication Date: 2021-02-09
- Inventor: Soon Wei Wang , Jin Yoong Liong , Chee Hiong Chew , Francis J. Carney
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/78 ; H01L21/56 ; H01L23/00 ; H01L25/00 ; H01L25/065 ; H01L21/3105 ; H01L23/492 ; H01L25/07 ; H01L25/18 ; H01L23/495

Abstract:
In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.
Information query
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