Invention Grant
- Patent Title: System and method for implementing verification IP for pre-silicon functional verification of a layered protocol
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Application No.: US17010643Application Date: 2020-09-02
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Publication No.: US10915693B2Publication Date: 2021-02-09
- Inventor: Kaustubh Kumar , Pavitra Balasubramanian
- Applicant: SILICONCH SYSTEMS PVT LTD
- Applicant Address: IN Karnataka
- Assignee: SILICONCH SYSTEMS PVT LTD
- Current Assignee: SILICONCH SYSTEMS PVT LTD
- Current Assignee Address: IN Karnataka
- Agency: Procopio, Cory, Hargreaves & Savitch LLP
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F30/394 ; G01R31/317 ; G06F115/08

Abstract:
An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.
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