Invention Grant
- Patent Title: Semiconductor devices having pad isolation pattern
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Application No.: US16580024Application Date: 2019-09-24
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Publication No.: US10910426B2Publication Date: 2021-02-02
- Inventor: Byungjun Park , Jinju Jeon , Younghwan Choi
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2019-0052311 20190503
- Main IPC: H01L27/146
- IPC: H01L27/146

Abstract:
A semiconductor device is described which includes a substrate, an interlayer insulating layer provided below the substrate and including a via pad therein, a through via located at least partially within a via hole passing through the substrate and a portion of the interlayer insulating layer, a connection pad on the substrate, and a pad isolation pattern formed in the substrate to be located around the connection pad and the through via. The pad isolation pattern includes a plurality of bent portions having protrusions and recesses when viewed from a top view. As a result, cracks may be prevented from forming or growing in the semiconductor device.
Public/Granted literature
- US20200350354A1 SEMICONDUCTOR DEVICES HAVING PAD ISOLATION PATTERN Public/Granted day:2020-11-05
Information query
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