Invention Grant
- Patent Title: Semiconductor device bonding area including fused solder film and manufacturing method
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Application No.: US16181383Application Date: 2018-11-06
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Publication No.: US10910331B2Publication Date: 2021-02-02
- Inventor: Masanori Shindo
- Applicant: LAPIS SEMICONDUCTOR CO., LTD.
- Applicant Address: JP Kanagawa
- Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee Address: JP Kanagawa
- Agency: Volentine, Whitt and Francos, PLLC
- Priority: JP2017-214885 20171107
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/683

Abstract:
A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
Public/Granted literature
- US20190139918A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2019-05-09
Information query
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