Invention Grant
- Patent Title: Microelectronic devices designed with capacitive and enhanced inductive bumps
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Application No.: US16464972Application Date: 2016-12-30
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Publication No.: US10910305B2Publication Date: 2021-02-02
- Inventor: Telesphor Kamgaing , Georgios C. Dogiamis , Sasha N. Oster
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/069622 WO 20161230
- International Announcement: WO2018/125241 WO 20180705
- Main IPC: H01L23/64
- IPC: H01L23/64 ; H01L23/522 ; H01G4/33 ; H01G4/38 ; H01L23/488 ; H01L23/50 ; H01L23/00 ; H01L49/02 ; H05K1/16

Abstract:
Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.
Public/Granted literature
- US20190326213A1 MICROELECTRONIC DEVICES DESIGNED WITH CAPACITIVE AND ENHANCED INDUCTIVE BUMPS Public/Granted day:2019-10-24
Information query
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