- Patent Title: High resistivity SOI wafers and a method of manufacturing thereof
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Application No.: US16058550Application Date: 2018-08-08
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Publication No.: US10910257B2Publication Date: 2021-02-02
- Inventor: Igor Peidous , Srikanth Kommu , Gang Wang , Shawn George Thomas
- Applicant: GlobalWafers Co., Ltd
- Applicant Address: TW Hsinchu
- Assignee: GlobalWafers Co., Ltd
- Current Assignee: GlobalWafers Co., Ltd
- Current Assignee Address: TW Hsinchu
- Agency: Armstrong Teasdale LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02 ; H01L29/06

Abstract:
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
Public/Granted literature
- US20180350661A1 HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF Public/Granted day:2018-12-06
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