Invention Grant
- Patent Title: CAM storage schemes and CAM read operations for detecting matching keys with bit errors
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Application No.: US16390370Application Date: 2019-04-22
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Publication No.: US10910057B2Publication Date: 2021-02-02
- Inventor: Idan Alrod , Eran Sharon , Alon Marcu , Yan Li
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Dickinson Wright PLLC
- Agent Steven Hurles
- Main IPC: G11C15/04
- IPC: G11C15/04 ; G11C8/08 ; G11C16/08 ; G06F16/903 ; G11C16/04 ; G11C16/34 ; G11C16/26

Abstract:
A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.
Public/Granted literature
- US20200335146A1 CAM STORAGE SCHEMES AND CAM READ OPERATIONS FOR DETECTING MATCHING KEYS WITH BIT ERRORS Public/Granted day:2020-10-22
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