- Patent Title: System and method for reducing power consumption of memory device
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Application No.: US16137305Application Date: 2018-09-20
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Publication No.: US10910055B2Publication Date: 2021-02-02
- Inventor: Futoshi Igaue
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2017-229304 20171129
- Main IPC: G11C15/04
- IPC: G11C15/04 ; G11C29/44 ; G11C29/38 ; G11C29/00 ; G11C29/02

Abstract:
The present invention provides a semiconductor device that can reduce the power consumption, including: a plurality of search memory cells arranged in a matrix; a plurality of match lines provided corresponding to each memory cell row to determine match/mismatch between data stored in the search memory cell and search data; a plurality of match line retention circuits provided corresponding to each of the match lines; a storage unit for storing information relating to the state of each of the match lines; and a selection circuit for selectively activating the match line retention circuits based on the information stored in the storage unit.
Public/Granted literature
- US20190164608A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-05-30
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