Invention Grant
- Patent Title: Memory system for restraining threshold variation to improve data reading
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Application No.: US16697540Application Date: 2019-11-27
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Publication No.: US10803953B2Publication Date: 2020-10-13
- Inventor: Masanobu Shirakawa , Marie Takada , Tsukasa Tokutomi , Yoshihisa Kojima , Kiichi Tachi
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@54dd5cc7
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/08 ; G11C16/34 ; H01L27/1157 ; G11C16/12 ; G11C16/26 ; G11C11/56 ; H01L27/11582 ; G11C16/10

Abstract:
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
Public/Granted literature
- US20200098431A1 MEMORY SYSTEM FOR RESTRAINING THRESHOLD VARIATION TO IMPROVE DATA READING Public/Granted day:2020-03-26
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