Invention Grant
- Patent Title: Integrated circuit packages and methods for forming the same
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Application No.: US16694349Application Date: 2019-11-25
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Publication No.: US10770366B2Publication Date: 2020-09-08
- Inventor: Chia-Wei Tu , Hsien-Wei Chen , Tsung-Fu Tsai , Wen-Hsiung Lu , Yian-Liang Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L21/78 ; H01L23/58
Abstract:
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
Public/Granted literature
- US20200091027A1 Integrated Circuit Packages and Methods for Forming the Same Public/Granted day:2020-03-19
Information query
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