A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.