Invention Grant
- Patent Title: Multiple-stage power amplifiers implemented with multiple semiconductor technologies
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Application No.: US16172561Application Date: 2018-10-26
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Publication No.: US10763792B2Publication Date: 2020-09-01
- Inventor: Joseph Gerard Schultz , Enver Krvavac , Olivier Lembeye , Cedric Cassan , Kevin Kim , Jeffrey Kevin Jones
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Agent Sherry W. Schumm
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@43508a38
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H03F1/56 ; H03F3/213 ; H03F3/195 ; H01L23/66 ; H03F3/24 ; H04B1/04 ; H01L29/20

Abstract:
A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.
Public/Granted literature
- US20190140598A1 MULTIPLE-STAGE POWER AMPLIFIERS IMPLEMENTED WITH MULTIPLE SEMICONDUCTOR TECHNOLOGIES Public/Granted day:2019-05-09
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