- Patent Title: Semiconductor wafer and method of inspecting semiconductor wafer
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Application No.: US15586526Application Date: 2017-05-04
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Publication No.: US10763332B2Publication Date: 2020-09-01
- Inventor: Hisashi Yamada , Taiki Yamamoto , Kenji Kasahara
- Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
- Applicant Address: JP Tokyo
- Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
- Current Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@563c93c2 com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@3df44d13 com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@68f5a4cc com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@659b7ea6
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L23/00 ; G01N23/20 ; H01L21/02 ; G01N23/20008 ; H01L29/778

Abstract:
Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1
Public/Granted literature
- US20170236906A1 SEMICONDUCTOR WAFER AND METHOD OF INSPECTING SEMICONDUCTOR WAFER Public/Granted day:2017-08-17
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