Invention Grant
- Patent Title: Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
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Application No.: US16261305Application Date: 2019-01-29
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Publication No.: US10763326B2Publication Date: 2020-09-01
- Inventor: Injo Ok , Balasubramanian Pranatharthiharan , Soon-Cheon Seo , Charan V. V. S. Surisetty
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/764 ; H01L21/762 ; H01L21/3105 ; H01L21/3213 ; H01L21/3065 ; H01L29/49 ; H01L23/485 ; H01L21/768 ; H01L21/8234 ; H01L23/532 ; H01L23/535 ; H01L27/088 ; H01L29/161

Abstract:
A method of forming a semiconductor structure includes forming a middle-of-line (MOL) oxide layer in the semiconductor structure. The MOL oxide layer including multiple gate stacks formed on a substrate. A nitride layer is formed over a silicide in the MOL oxide layer. At least one self-aligned contact area (CA) element is formed within the nitride layer. The MOL oxide layer is selectively recessed on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and a nitride. A nitride cap of the plurality of gate stacks is selectively recessed. An air-gap oxide layer is deposited for introducing one or more air-gaps in the deposited air-gap oxide layer. The air gap oxide layer is reduced to the at least one self-aligned CA element and the nitride layer.
Public/Granted literature
- US20190157388A1 MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK Public/Granted day:2019-05-23
Information query
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