The present disclosure provides a semiconductor structure, including a memory region and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first Nth metal line, and a first (N+1)th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1)th metal via having a first height. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line and having a second height. N is an integer greater than or equal to 1 and the first height is greater than the second height. A method of manufacturing the semiconductor structure is also disclosed.