Invention Grant
- Patent Title: MOS antifuse with void-accelerated breakdown
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Application No.: US15327338Application Date: 2014-08-19
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Publication No.: US10763209B2Publication Date: 2020-09-01
- Inventor: Roman Olac-Vaw , Walid Hafez , Chia-Hong Jan , Hsu-Yu Chang , Ting Chang , Rahul Ramaswamy , Pei-Chi Liu , Neville Dias
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2014/051618 WO 20140819
- International Announcement: WO2016/028266 WO 20160225
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L23/525 ; H01L29/423 ; H01L29/66 ; G11C17/16 ; H01L21/768 ; H01L27/112

Abstract:
A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.
Public/Granted literature
- US20170162503A1 MOS ANTIFUSE WITH VOID-ACCELERATED BREAKDOWN Public/Granted day:2017-06-08
Information query
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