Invention Grant
- Patent Title: Method of manufacturing semiconductor apparatus
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Application No.: US16268955Application Date: 2019-02-06
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Publication No.: US10763171B2Publication Date: 2020-09-01
- Inventor: Eiichi Yamamoto , Takahiko Mitsui
- Applicant: OKAMOTO MACHINE TOOL WORKS, LTD.
- Applicant Address: JP Gunma
- Assignee: OKAMOTO MACHINE TOOL WORKS, LTD.
- Current Assignee: OKAMOTO MACHINE TOOL WORKS, LTD.
- Current Assignee Address: JP Gunma
- Agency: Rankin, Hill & Clark LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@3ddfe314
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/762 ; H01L25/00 ; H01L25/065

Abstract:
An embodiment of the present disclosure provides a method of manufacturing a semiconductor apparatus, including the following steps. A) forming a semiconductor device element in a Si active layer of an insulating isolation Si substrate including the Si active layer, a buried insulating layer, and a Si supporting substrate arranged in this order; B) forming a plurality of through electrode holes penetrating the Si active layer and the buried insulating layer to reach a partial region of the Si supporting substrate in an element region layer including the formed semiconductor device element; C) forming a through silicon via by sequentially forming an insulating film, a barrier film, and a Cu film inside the through electrode hole to completely fill the through electrode hole; D) forming a multilayer wiring layer including a wiring layer connected to the semiconductor device element on an outer surface of the element region layer in which the through silicon via is formed; and E) exposing the Cu film of the through silicon via by removing the Si supporting substrate after forming the multilayer wiring layer.
Public/Granted literature
- US20190244858A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2019-08-08
Information query
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