Invention Grant
- Patent Title: Wafer flatness control using backside compensation structure
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Application No.: US16140463Application Date: 2018-09-24
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Publication No.: US10763099B2Publication Date: 2020-09-01
- Inventor: Xiaowang Dai , Zhenyu Lu , Qian Tao , Yushi Hu , Ji Xia , Zhaosong Li , Jialan He
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: Bayes PLLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; G03F7/20 ; H01L21/302 ; H01L21/66 ; H01L23/00

Abstract:
Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.
Public/Granted literature
- US20200058486A1 WAFER FLATNESS CONTROL USING BACKSIDE COMPENSATION STRUCTURE Public/Granted day:2020-02-20
Information query
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