Invention Grant
- Patent Title: Resistive change element arrays using a reference line
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Application No.: US16458484Application Date: 2019-07-01
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Publication No.: US10762961B2Publication Date: 2020-09-01
- Inventor: Claude L. Bertin
- Applicant: Nantero, Inc.
- Applicant Address: US MA Woburn
- Assignee: Nantero, Inc.
- Current Assignee: Nantero, Inc.
- Current Assignee Address: US MA Woburn
- Agency: Nantero, Inc.
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00 ; G11C13/02 ; G11C23/00 ; G11C29/02 ; H03K19/17728 ; H03K19/17736 ; H03K19/1776 ; H03K19/1778 ; H03K19/17796 ; B82Y10/00 ; G11C7/14

Abstract:
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.
Public/Granted literature
- US20190341107A1 Resistive Change Element Arrays Using a Reference Line Public/Granted day:2019-11-07
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