A memory system includes a storage device and a controller. The storage device includes a first string including a first memory cell transistor and a second memory cell transistor connected in series to each other, and a first select transistor, a second string including a third memory cell transistor and a second select transistor, a gate of the second select transistor being independent from a gate of the first select transistor. The controller configured to perform first writing to cause a threshold voltage of the first memory cell transistor to be lower than a first target threshold voltage, perform second writing to cause a threshold voltage of the second memory cell transistor to be higher than a second target threshold voltage after the first writing, perform third writing to cause a threshold voltage of the first memory cell transistor to be higher than the first target threshold voltage after the second writing, and perform fourth writing on the third memory cell transistor after the third writing.