Invention Grant
- Patent Title: System and method to control memory failure handling on double-data rate dual in-line memory modules
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Application No.: US15903844Application Date: 2018-02-23
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Publication No.: US10761919B2Publication Date: 2020-09-01
- Inventor: René Franco , Amit S. Shah , Tuyet-Huong Thi Nguyen , Vijay B. Nijhawan , Vadhiraj Sankaranarayanan , Mark L. Farley , Andrew Butcher
- Applicant: DELL PRODUCTS, LP
- Applicant Address: unknown Round Rock
- Assignee: Dell Products, L.P.
- Current Assignee: Dell Products, L.P.
- Current Assignee Address: unknown Round Rock
- Agency: Larson Newman, LLP
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F3/06 ; G06F11/10 ; G11C16/00

Abstract:
An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.
Public/Granted literature
- US20190266036A1 System and Method to Control Memory Failure Handling on Double-Data Rate Dual In-Line Memory Modules Public/Granted day:2019-08-29
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