Invention Grant
- Patent Title: Method to handle corrected memory errors on kernel text
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Application No.: US15955747Application Date: 2018-04-18
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Publication No.: US10761918B2Publication Date: 2020-09-01
- Inventor: Aravinda Prasad , Mahesh J. Salgaonkar
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Robert J. Shatto
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F11/10 ; G06F9/54 ; G06F9/455 ; G06F9/30

Abstract:
Embodiments of the present invention facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in a physical error location of a memory and a kernel function impacted by the CE. The identified kernel function includes a plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in a first region of the memory. The first region includes the physical error location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory. The first physical memory location in the first region of the memory is updated to include an instruction to branch to the second physical memory location in the second region of the memory.
Public/Granted literature
- US20190324830A1 METHOD TO HANDLE CORRECTED MEMORY ERRORS ON KERNEL TEXT Public/Granted day:2019-10-24
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