Invention Grant
- Patent Title: Multi-level wear leveling for non-volatile memory
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Application No.: US16110739Application Date: 2018-08-23
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Publication No.: US10761739B2Publication Date: 2020-09-01
- Inventor: Ying Yu Tai , Ning Chen , Jiangli Zhu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/10

Abstract:
A memory sub-system performs a first wear leveling operation among a plurality of individual data units of the memory component after a first interval and performs a second wear leveling operation among a first plurality of groups of data units of the memory component after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units. The memory sub-system further performs a third wear leveling operation among a second plurality of groups of data units of the memory component after a third interval, wherein a second group of the second plurality of groups comprises the first plurality of groups of data units.
Public/Granted literature
- US20200065007A1 MULTI-LEVEL WEAR LEVELING FOR NON-VOLATILE MEMORY Public/Granted day:2020-02-27
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