A detector assembly is provided that includes a semiconductor detector, a collimator, and a processing unit. The semiconductor detector has a first surface and a second surface opposed to each other. The first surface includes pixelated anodes, and the second surface includes a cathode electrode. The collimator includes openings defined by septa. The collimator defines a pitch D between adjacent septa, with the septa defining a septa length L. A ratio of L/D is less than 14. The processing unit is configured to identify detected events within virtual sub-pixels distributed along a length and width of the semiconductor detector. Each pixel comprises a plurality of corresponding virtual sub-pixels, and absorbed photons are counted as events in a corresponding virtual sub-pixel.