Invention Grant
- Patent Title: Gate spacer and method of forming
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Application No.: US16663891Application Date: 2019-10-25
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Publication No.: US10741662B2Publication Date: 2020-08-11
- Inventor: Chun Hsiung Tsai , Kuo-Feng Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L21/02 ; H01L21/311 ; H01L21/8234 ; H01L21/8238 ; H01L21/3105 ; H01L21/28 ; H01L29/165

Abstract:
Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.
Public/Granted literature
- US20200058754A1 GATE SPACER AND METHODS OF FORMING Public/Granted day:2020-02-20
Information query
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