Invention Grant
- Patent Title: Formation of dislocations in source and drain regions of finFET devices
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Application No.: US16210305Application Date: 2018-12-05
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Publication No.: US10741642B2Publication Date: 2020-08-11
- Inventor: Chun Hsiung Tsai , Wei-Yuan Lu , Chien-Tai Chan , Wei-Yang Lee , Da-Wen Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/02 ; H01L29/08 ; H01L29/78 ; H01L29/66 ; H01L29/417 ; H01L29/16 ; H01L29/32 ; H01L29/04 ; H01L29/06 ; H01L29/165

Abstract:
Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
Public/Granted literature
- US20190115428A1 Formation of Dislocations in Source and Drain Regions of FinFET Devices Public/Granted day:2019-04-18
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