Invention Grant
- Patent Title: Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory
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Application No.: US16427176Application Date: 2019-05-30
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Publication No.: US10741566B2Publication Date: 2020-08-11
- Inventor: Debra M. Bell
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11
- IPC: H01L27/11 ; G11C11/41 ; G11C11/419 ; G11C11/412 ; H01L27/092
Abstract:
Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.
Public/Granted literature
- US20190393227A1 Integrated Arrangements of Pull-Up Transistors and Pull-Down Transistors, and Integrated Static Memory Public/Granted day:2019-12-26
Information query
IPC分类:
