- Patent Title: Correction of mismatch errors in a multi-bit delta-sigma modulator
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Application No.: US16532198Application Date: 2019-08-05
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Publication No.: US10735021B2Publication Date: 2020-08-04
- Inventor: Marie Hervé
- Applicant: SCALINX
- Applicant Address: FR Paris
- Assignee: SCALINX
- Current Assignee: SCALINX
- Current Assignee Address: FR Paris
- Agency: Stoel Rives LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4f402242
- Main IPC: H03M3/00
- IPC: H03M3/00

Abstract:
A method for calibrating a multi-bit Delta-Sigma modulator is disclosed herein. The method includes at least one main multi-bit digital-analogue converter in a return loop for generating a return signal subtracted from an input of the modulator. The main converter includes a plurality of elementary source cells at least some of which, referred to as active cells, are associated with the various input bits of the converter for generating the return signal. The output level of these active source cells is adjustable under the action of a matching signal that comes from a calibration circuit receiving an output signal from the modulator at its input. The calibration circuit includes a generator of a calibration sequence.
Public/Granted literature
- US20200067521A1 CORRECTION OF MISMATCH ERRORS IN A MULTI-BIT DELTA-SIGMA MODULATOR Public/Granted day:2020-02-27
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